1. Field of the Invention
The present invention relates to a flash type analog to digital (A/D) converting circuit, and more particularly, to a layout method of a comparator array for a flash type A/D converting circuit.
2. Description of Related Art
A conventional flash type analog to digital (A/D) converting circuit includes a reference voltage generating circuit, a thermometer code generating circuit, and an encoder. The reference voltage generating circuit includes a quantity 2n of resistors, and the thermometer code generating circuit includes a comparator array having (2n−1) comparators.
In a layout method of the 2n resistors and the (2n−1) comparators of the conventional flash type A/D converting circuit, the 2n resistors are folded in two rows in order to gather a reference voltage input terminal and an analog signal input terminal. So, the (2n−1) comparators are not arranged in order but in turn.
When the (2n−1) comparators undergo a state transition, respective neighboring comparators also undergo a state transition. Here, by the layout method described above, a digital signal output from the neighboring comparators do not remain at to the same state but transit to a different state. As a result, since the neighboring comparators adjacent to the comparators affect operation of the comparators to thereby increase an offset voltage of the comparators, an accurate digital signal cannot be generated.
Even though a dummy element or metal can be added to remove such a problem, there is a problem in that this increases a layout area size.